In conducting a test on a large-scale integrated circuit (LSI) chip, a high-speed test (transition delay test (TDT)) executed at LSI system operation speed has been demanded in addition to stuck-fault tests. Typically, a gated clock technique is employed to stop an LSI from supplying a clock signal to a circuit block that does not need to operate at the time of system operation (user mode operation).
FIG. 11 depicts a circuit configuration of an LSI before test synthesis. As depicted in FIG. 11, the circuit 1 of the LSI includes multiple gated clock buffers 2a and 2b, a phase-locked loop (PLL) circuit 3 that supplies a clock signal to each of the gated clock buffers 2a and 2b, multiple circuit blocks 6a and 6b each of which is supplied with a clock signal from the gated clock buffers 2a and 2b and has a flip-flop 4 and a memory 5, and enable control circuits (EN Logic) 7 respectively controlling the gated clock buffers 2a and 2b. 
In the configuration depicted in FIG. 11, for example, when one circuit block 6a operates while another circuit block 6b does not operate at the time of system operation, the gated clock buffer 2a connected to the operating circuit block 6a supplies the clock signal to the circuit block 6a while the gated clock buffer 2b connected to the non-operating circuit block 6b stops the supply of the clock signal to the circuit block 6b. 
FIG. 12 depicts a circuit configuration of an LSI after test synthesis performed according to a conventional test method. As depicted in FIG. 12, a design for test (DFT) controller 8, mask circuits 9, and a selector 10 for PLL bypass are incorporated in the circuit 1 of the LSI as a result of the test synthesis. Each mask circuit 9 is interposed between an enable control circuit 7 and an enable control terminal EN of each of the gated clock buffers 2a and 2b. When a test is conducted, the DFT controller 8 keeps all mask circuits 9 in an active state. As a result, the flip-flops 4 and the memories 5 of all the circuit blocks 6a and 6b are constantly supplied a clock signal, which means that the entire LSI operates substantially at the same time.
A semiconductor integrated circuit having a scan test circuit is known as an integrated circuit utilizing the gated clock technique. For example, the semiconductor integrated circuit includes a logic circuit, a flip-flop circuit that receives a signal output from the logic circuit and synchronized with a clock signal, and a mask circuit that generates a clock stopping signal for stopping supply of the clock signal to the flip-flop circuit. The semiconductor integrated circuit has a function of scan testing in which a scan path is formed by the logic circuit and the flip-flop circuit. In a normal operation mode, the mask circuit stops the supply of the clock signal to the flip-flop circuit. In a scan test mode, the supply of the clock signal to the flip-flop circuit is enabled regardless of the operation of the mask circuit, so that the flip-flop circuit forms a scan path for a scan test on the mask circuit (see Japanese Laid-Open Patent Publication No. 2006-38831).
As described, an entire LSI operates substantially simultaneously in a test according to a conventional test method and operates at higher speed in a high-speed test. Because of this, power consumption at the time of testing becomes greater than power consumption at the time of system operation, which may result in a large voltage drop. Usually, power supply design for the LSI is determined with consideration of the amount of voltage drop occurring during system operation, etc., so that the LSI operates trouble-free at the time of system operation. This leads to a problem in that if a voltage drop larger than a voltage drop occurring during system operation occurs during a high-speed test, the high-speed test cannot be conducted.